1. Field of the Invention
This invention relates to a serial access semiconductor memory device having a redundancy system, and particularly to a semiconductor memory device in which a column redundancy is employed for replacing defective data.
2. Description of the Prior Art
As a semiconductor memory device such as an video memory, there is known a memory device arranged to perform a serial inputting and outputting operation. The memory device performing such serial input-output operation usually has a serial memory (serial access port) of a word scale equal to the number of memory cells of a row of the memory core or a fraction thereof.
FIG. 1 shows an example of the memory device having the usual serial memory. In one portion of a memory cell array 101 having memory cells arranged in a matrix configuration, a row redundant section 102 and a column redundant section 103 are provided for substituting the defective bits and improving the yield. The row redundant section 102 is extended along the extending direction of the word line and Row-selected by a word line WL.sub.R selected by a row decoder 104. On the other hand, the column redundant section 103 is extended along the extending direction of the bit line. A usual word line WL is used for row selection of the column redundant section 103. Data on the memory cell array 101 are amplified by a sense amplifier 105 over bit line and inputted or outputted in parallel between the array and a serial memory 106. This serial memory 106 has the function of transiently storing data and of serial-parallel or parallel-serial conversion and is constituted by a plurality of stages of flip-flops with selectors connected in-between. The serial memory 106 is adapted to input or output data in series to or from the input-output circuit.
Meanwhile, with the memory apparatus provided with such serial memory, since data are inputted and outputted to or from the memory cell array in parallel, a problem is raised as to how data from the column redundant section 103 is to be exchanged. In connection with such problem, the present Applicant proposed a technique of exchanging the defective bits and the redundant bits in the column redundant section as disclosed in Japanese Patent Application No. 1(1989)-247828. According to this technique, a switching circuit is provided in a parallel data bus between the memory cell array and the serial memory to perform a switching between the column redundant section and the redundant bus.
In the technique of bus exchange, comparison between the defective address and the current address becomes necessary and an address comparator circuit is used for this purpose. The address comparator circuit for generating the exchange signal is constructed as shown for example in FIG. 2. This address comparison circuit is explained briefly. A plural of fuse 11 that may melt on laser irradiation are connected in parallel with a node 110, and a plural of MOS transistor 112, to each gate of which a read-out address signal or its complementary address signal is entered, are provided respectively between the grounding line and the other end of the fuse 111. Either the address side A.sub.0, A.sub.1 on the complementary side A.sub.0, A.sub.1 of the fuse 111 melts bit-by-bit in accordance with the defective address. The node 110 is connected to a source voltage Vcc via pMOS transistor 113, and is precharged to a source voltage Vcc when the pMOS transistor 113 is turned on by control signal .phi.P. With this address comparator, the potential at the node 110 is maintained as it is, without being lowered, when the read-out address signal and its complementary address signal completely coincides with the melting pattern of the fuse 111. In case of non-coincidence, the potential at the node 110 is lowered due to discharging via fuse 111 and MOS transistor 112, so that the output of the inverter 114 is raised. This signal is supplied as the switching signal between the redundant bus and the parallel data bus.
In general, in a mega-bit class DRAM, redundancy of the order of four columns is effective and it becomes necessary to make a switching between a plurality of redundant columns. In an image memory, the multi-bit construction is a principle, so that, when it is considered that the parallel-to-serial conversion section is distributed on the chip, it is not always effective to make a switching between the parallel data bus and the redundant bus.
That is, in a technique of switching between the parallel data bus and the redundant bus, switching signals become necessary for its control, and an address comparison circuit making use of a fuse is necessitated for generating the switching signal. When two or more redundant columns are switched on the bus-to-bus basis, it becomes necessary to provide a number of switching circuits consistent with the redundant columns in series which number is equal to the number of the redundant columns. Therefore, the scale of the changeover circuit is drastically increased to complicate the generation of the switching signals. In case of a multi-bit construction, it becomes necessary to provide the switching circuit for each parallel-to-serial converting section to increase further the circuit scale.
When each serial memory of the video memory having a plurality of serial memories are to be operated asynchronously, the read-out or write address need to be compared to the defective address independently. In the case of utilizing the address comparator circuit shown in FIG. 2, the fuse 111 and the MOS transistor 112 to which the addresses are entered, are inseparable. An address comparator circuit need to be provided for each serial memory and the number of method fuse is also increased with the number of the serial memories.